‘Two wafers are better than one’ for 3D flash
As flash memory makers struggle with a collapsing market, Siva Sivaram, president of technology and strategy at Western Digital, set out at the recent VLSI Symposium the ways in which they can restore margins and sales in the face of major issues with cost. The approach the storage company has taken with Kioxia may have some lessons on the trajectory of 3D extensions to future logic processes.
Despite being a “rare secular growth market” Sivaram explained the mismatch between the successive reductions in price-per-gigabyte that drive this steady growth and the problems of delivering the capacity. “We are in the middle of the worst downturn but the bounceback will be equally fast.”
A little over a decade ago, the industry stopped being dependent on advances in lithography to increase bit density. “It’s not something that you normally see in semiconductor,” Sivaram said.
When cell-cell interference became too troublesome, the NAND flash industry switched to 3D structures so it could use larger cells but still grow the bit count. The vertical strings are now more than 100 layers deep with double stacks used to push vertical cell counts past 200. In principle, this process could continue past a thousand. In practice, economics get in the way.
Sivaram compared the average cost reductions and growth rates for bits across four of the 2D generations and four of the newer 3D versions. Though the move to 3D saw bit growth jump from 27 per cent per node to 39, code reductions did not see the same benefit. Instead rather than each successive node leading to a cost reduction of 24 per cent, it fell to just 11 per cent for the 3D generations. “When we had cost reductions per generation of 24 per cent, everyone was happy,” he said. But with costs scaling by a little over 10 per cent per generation, in order to sell products vendors have at times, such as most recently, given bits away. “That causes the industry problems.”
Expensive towers
Vertical scaling is not the only vector for bit growth, Sivaram explained. Logical scaling by increasing the number of stored bits per cells has the greatest payoff but with 4bit cells now in production, further gains are more difficult to achieve. Lateral scaling, a return to classical semiconductor areal scaling, and architectural scaling where circuits are moved around to consume less die area offer potentially good bit-growth and bit-cost tradeoffs. But at the current level of technology, “vertical scaling is the worst thing you can do”, he claimed. “You need to balance how to shrink laterally while growing the number of layers and this is what the industry is doing.”
The latest, eight, generation of flash developed with Kioxia has taken advantage of a major change in processing to benefit from architectural scaling. The companies have opted for the CMOS-under-array (CUA) approach where read and write transistors are placed directly under the flash layers they need to access and control rather than the traditional approach of laying them out next to the arrays, which eats into the space available for memory bits. The problem with CUA is that thermal processing that would be ideal for flash cells disrupts advanced CMOS transistors.
“Transistors never advanced beyond 1995 levels because the thermal processing would kill them,” Sivaram claimed. This tends to lead to oversized, slow circuits that are difficult to match in size to the flash arrays sitting over them. To get around the problem, Kioxia and Western Digital turned to the technology of wafer bonding with mixed-signal and memory circuitry processed separately before being brought together and finished. “It’s clear it increases as you have two wafers but it enables things that reduce cost,” Sivaram argued. “The I/O is faster, the approach reduces processing complexity, and the more advanced transistors allow the overhead area to be shrunk.”
The improved circuitry can access more of the memory strings, which allows for greater lateral scaling in the array itself. “I’m willing to spend a bit more on the two wafers in a way that allows me to shrink laterally more than was possible before.”
