16nm

February 28, 2019

Graphcore licenses ESD protection from Sofics

Graphcore has licensed IP from Belgium-based Sofics to protect its Colossus GC2 processors from ESD.
Article  |  Topics: Blog - IP  |  Tags: , , ,
December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
July 30, 2015

10nm flow reveals complexity of finFET design process

Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,
June 5, 2014

Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond

Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore's law scaling
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , , ,   |  Organizations:
April 16, 2014

FinFET variability issues challenge advantages of new process

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
November 13, 2013

TSMC succession plan emphasizes stability

TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , , , ,   |  Organizations: , , ,
October 1, 2013

TSMC 16nm finFET, Ge 20nm p-finFET set for IEDM

TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , , , ,   |  Organizations: ,
May 29, 2013

TSMC and Xilinx forge tighter bonds to speed up finFET port

Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).
Article  |  Topics: Blog - EDA, Embedded, PCB  |  Tags: , , ,   |  Organizations: ,
March 20, 2013

DATE: Double patterning and finFETs force flexibility on tools

EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:

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