Mentor, a Siemens business, has unveiled a test platform for the embedded MRAM (eMRAM) compiler IP being offered ARM and Samsung on a 28nm FDSOI process.
The use of FDSOI has a range of advantages that promote eMRAM alongside other non-volatile memory options. The process technology supports reverse and forward body-biasing to reduce leakage and boost performance, respectively. These qualities are a good fit with the demands being placed on embedded non-volatile memory in markets such as automotive, AI and the Internet of Things.
At the same time, FDSOI raises its own test challenges that require dedicated sotutions. Some of these are attributed to the probabilistic nature of the new physics and different failure modes associated with the process.
Mentor’s new test platform, based on its Tessent suite, is based upon the results of a Samsung/ARM test-chip collaboration, using the results to expand and refine the built-in-self-test capabilities. Specifically, it is designed to increase memory yield by combining spare resources and multi-bit ECC logic through the use of new hardware and test algorithms.
The platform also includes Tessent’s automated trimming functionality, a more established technique that the partners hope will help ease mainstream adoption of eMRAM throughout the industry.
ARM and Samsung announced the 28nm FDSOI eMRAM in 2018. Earlier this year, they said they were extending collaboration to include the delivery of complier IP for an 18nm process.