Breker adds automated system integration test generation for RISC-V

By TDF Editor |  No Comments  |  Posted: December 10, 2019
Topics/Categories: Blog - EDA, IP, - Verification  |  Tags: , , , , , , , , ,  | Organizations: , ,

Further evidence of the growing ecosystem around RISC-V comes today with Breker Verification Systems’ launch of an automated test content generator the open-source processor platform.

The app is the latest addition to the company’s Trek5 family and, as with most of Breker’s tools, leverages the Portable Stimulus Standard (PSS), which is also enjoying increasing adoption.

The RISC-V TrekApp targets unpredictable corner cases and seeks to greatly reduce the need for extensive manual test writing. The company says that users do not need to learn the PSS language themselves to leverage its benefits. The app is complaint with the Universal Verification Methodology (UVM) and use in software-driven verification environments.

“Breker’s RISC-V TrekApp builds on our success with other processors to fully automate this intensive task while allowing for the distinctiveness created by RISC-V,” said Adnan Hamid, Breker’s president and CEO.

The app was developed in cooperation with leading RISC-V IP and silicon provider SiFive and has been validated on its processors.

Inside the RISC-V TrekApp

App features include interrupt mechanism testing, modular instruction extension verification and links to multiple compliance test suites. The debug environment highlights tests that fail, including memory map and key register detail, and interfaces with common debuggers such as Synopsys’ Verdi SoC Debug Platform for extended analysis.

A cache coherency test suite enables automated systematic testing of data consistency and cache state transitions across all caches (L1/L2/L3 snoop filters) for multi-core/multi-cluster designs with I/O coherent interfaces such as PCI Express.

Integration with fabrics, memory controllers (DDR and HBM) are stress-tested as are atomic and other special memory accesses.

For instruction extension verification, verification tests can be written in PSS, SystemVerilog, UVM and/or C/C++. These tests can be amalgamated with the system integration test suite scenario examination to confirm that no additional instructions will impair operation of the SoC.

Breker is launching the app to coincide with the start today (December 10) of the RISC-V Summit at the San Jose Convention Center. The app is available immediately with pricing upon request.

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