SiFive


December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
June 18, 2019

RISC-V firms aim for lower-cost design starts

Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations: , , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors