SiFive


September 24, 2021

Siemens brings chip-design flow to DARPA Toolbox Initiative

Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: , , , ,
February 15, 2021

Getting a RISC-V embedded toolchain in place

A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
Article  |  Topics: Blog - Embedded, - Next Generation Design, Standards  |  Tags: , ,   |  Organizations: ,
November 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
June 18, 2019

RISC-V firms aim for lower-cost design starts

Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations: , , , ,

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