ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Cutting the cabling to simplify the emulation process.
Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
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