RTL

June 18, 2013

Real Intent highlights hierarchical clock domain crossing with Meridian 5.0

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
April 25, 2012

No more spaghetti

Cutting the cabling to simplify the emulation process.
Article  |  Topics: Commentary, Design to Silicon, Blog - EDA, - Industry Blogs  |  Tags: ,   |  Organizations:
April 25, 2012

Mentor unveils second-generation Veloce emulator

Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , ,   |  Organizations:

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