Real Intent highlights hierarchical clock domain crossing with Meridian 5.0
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
RTL
No more spaghetti
Cutting the cabling to simplify the emulation process.
Mentor unveils second-generation Veloce emulator
Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.