Arteris extends safety and speed for NoC

By Chris Edwards |  No Comments  |  Posted: March 18, 2024
Topics/Categories: Blog - IP  |  Tags: , , , , , ,  | Organizations:

Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.

Arteris has added support for CHI-E to the existing CHI-B, ACE, ACE-Lite and AXI interconnect standards in the Ncore lineup. Able to support a range of topologies up to large meshes, Ncore has received a number of updates in the latest release to improve performance, include a larger number of replacement policies for cache-coherent operation, boost debug capabilities, and help ensure functional safety.

The approach Arteris took with Ncore from it initial launch was to provide a flow-based approach to designing with on-chip networks that can support cache-coherent transfers between processors and accelerators. Designers enter their chip specifications, make architecture choices, have the NoC library elements automatically mapped, and then refine the design before generating the final RTL. The company argues this ordering of tasks saves large amounts of time overall and reduces project risk.

One of the earlier adopters of the Arteris NoC architecture is Mobileye. “We have worked with Arteris network-on-chip technology since 2010, using it in our advanced autonomous driving and driver-assistance technologies,” said Leonid Smolyansky, senior vice president of SoC architecture, security and safety at the autonomous-driving IC supplier. “We are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerance and reliable SoC design.”

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