variability


December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: , ,
May 25, 2015

Shape a major choice for sub-10nm nanowire FETs

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
October 28, 2014

imec and Coventor partner for 7nm process development

Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
Article  |  Topics: Design to Silicon  |  Tags: , , , ,   |  Organizations: ,
July 25, 2014

GlobalFoundries licenses atomistic TCAD simulator toolchain

Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
April 16, 2014

FinFET variability issues challenge advantages of new process

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
May 28, 2013

Fabless, IP designers need process simulation tools, says Coventor CTO

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
Article  |  Topics: Design to Silicon, Blog - IP  |  Tags: , , ,   |  Organizations:
May 15, 2013

SureCore picks up grant for low-power, nanometer SRAM IP

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
Article  |  Topics: Blog Topics, Design to Silicon, Verification  |  Tags: , , , , ,   |  Organizations:
March 20, 2013

DATE: The real causes of carbon nanotube FET performance variation

Don't underestimate the influence of metallic nanotubes and tube alignment, say Stanford researchers.
October 11, 2012

Is your 20nm process gate-last? Maybe it should be

Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors