December 7, 2015
Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
May 25, 2015
TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
October 28, 2014
Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
July 25, 2014
Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
April 16, 2014
Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
May 28, 2013
Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
May 15, 2013
Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.
April 10, 2013
The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
March 20, 2013
Don't underestimate the influence of metallic nanotubes and tube alignment, say Stanford researchers.
October 11, 2012
Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.