Asymmetric variability issues could impact 7nm processes

By TDF Staff |  No Comments  |  Posted: December 7, 2015
Topics/Categories: Conferences, Design to Silicon  |  Tags: , , ,  | Organizations: , ,

New variability issues highlighted by a massive process simulation exercise could make it more difficult than expected to achieve the performance advantages of emerging 7nm and 5nm processes.

Nano-electronics research centre imec has worked with Coventor to simulate the process variability of its 7nm BEOL fabrication processes using Coventor’s SEMulator3D virtual fabrication platform. The simulation of a full process window, looking at how multiple parameters of multiple processes interact, would have taken one million wafers to complete using conventional methods.

Although detailed findings are currently reserved for imec development partners, David Fried, CTO – semiconductor, Coventor, commented: “One of the very interesting findings is that variations specs significantly tighter than expected will be required for 7nm manufacturing, and some of these specifications may need to be asymmetric. This can also lead to impacts on developing the unit processes or fabrication equipment itself.”

Asked about the viability of extracting useful advantages from 7nm processes, despite the potential need to derate their design characteristics to take into account variability, Fried said: “In my view, we can make 7nm and 5nm technologies that are controlled and high-performance, so as to make the transitions to these technologies worthwhile.

“However, in order to make these transitions, we need to fundamentally focus on processes and integration schemes that significantly improve the circuit density per wafer-cost. There are plenty of ways to fabricate technologies on these dimensions, but some of those ways will add so much cost, restrict area scaling so much, or degrade the performance distribution so badly, [as] to defeat the purpose.”

Fried promised to discuss these issues in more depth at a reception Coventor is hosting on Tuesday evening during this week’s International Electron Device Meeting in Washington DC.

An Steegen, senior vice president of process technology at imec, said: “Our collaboration is helping the semiconductor industry lower the risks associated with moving to the latest process technologies by providing customers with proven, tested process development platforms and advancing the availability, yield and cost of next-generation semiconductor technology.”

imec and Coventor have been using SEMulator3D to model imec’s 7nm process and analyze its variability for logic-only devices for a year, and have now extended their work to include 3D NAND Flash, STT-MRAM, and other device types.

The simulation has been enabled by the availability of a fully codified process model for the imec 7nm process flow, lots of servers to run the simulations at imec, and, according to Fried, “the development of a novel scheme for submitting experiments on specific process-variation combinations (not just full factorial), so as to map the process windows in an efficient way.”

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