III-V


May 12, 2017

Advanced processes feature at VLSI in June

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
September 30, 2015

Vertical structures to debut at IEDM 2015

A novel approach to 3D NAND will be among the presentations at the International Electron Device Meeting to be held in Washington, DC in December.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
May 11, 2015

VLSI Symposia delve into future process choices

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,
December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
November 20, 2013

FinFETs’ III-V future promises sub-7nm, RF and opto CMOS

FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: ,   |  Organizations:
October 5, 2012

IEF: Process kits for processes that don’t yet exist

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations:

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