Continental

November 12, 2015

DVCon Europe: UVM-SystemC backers ready first draft

But the bridge standard's European backers still need greater support from the big EDA vendors.

Article | Topics: Commentary, Conferences, Blog - EDA, Embedded, - ESL/SystemC, Verification | Tags: System Verilog, UVM, virtual prototyping | Organizations: Cadence Design Systems, Continental, Doulos, DVCon Europe, Fraunhofer Institute, Infineon Technologies, Magillem Design Services, NXP Semiconductors