Charting out the roadmap for FD-SOI

By Chris Edwards |  1 Comment  |  Posted: March 11, 2015
Topics/Categories: Blog - EDA  |  Tags: , , , , , , ,  | Organizations: , ,

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond. As those plans are drawn up, researchers at CEA as well as at foundry GlobalFoundries are working on bringing non-volatile memory and better RF support to the 28nm process.

Carlo Reita, director of nanoelectronics technical marketing and strategy at CEA-Leti, described at the DATE conference in Grenoble, France the plans the research institute has for FD-SOI to follow on from the 28nm process that GlobalFoundries and recent licensee Samsung Semiconductor are beginning to bring to production.

“For us, 28nm is in production,” Reita said. “So we are working on 14nm together with ST and beginning to concentrate on 10nm FD-SOI. We already have some preliminary results that it’s scalable down to 10nm.”

Reita said the 10nm process will scale the contacted poly pitch down from the 90nm set for the 14nm process to 64nm. “We will move from a gate-first process to gate-last. But the channel will still be undoped so variation will be minimal. We expect that it will be a cheaper process than what is being done for other technologies even when the cost of the substrate is taken into account.”

On the way to nanowire

Assuming that 10nm makes it into production, Reita argued that the roadmap for FD-SOI will marry up with the likely plan for finFETs. “In our vision for the future, we believe that below 10nm both planar and finFET will have to converge on nanowire. The core processes we use for planar can be used for nanowires.”

In common with Intel, which has suggested that the 7nm node and possible successors will need to use III-V, Reita said: “We are also starting to include new materials for the nanowires.”

A further possibility for integration is monolithic 3DIC, which CEA-Leti calls CoolCube. “We are currently working on 28nm and 14nm nodes. We are collaborating with people like Qualcomm, IBM and ST. It will be a big breakthrough if we can solve some technology challenges that are still open.”

Work is continuing on derivatives of the current 28nm process, said Laurent Remont, vice president of technology and strategy at ST, in his keynote at DATE: “There are derivatives going on that will optimise RF, support ultralow-voltage operation and add embedded non-volatile memory.

Incorporating RF

Although CEA-Leti has presented work on RF designs using FD-SOI, including at the most recent ISSCC, Reita said the improved RF process that can take Fmax to 350GHz. Gerd Teepe, director of design enablement for GlobalFoundries, said there are opportunities to use the back-biasing that is currently mostly aimed at altering digital behavior to improve RF designs. He pointed to the RF mixer as one component that could make good use of two gates to improve performance.

Flash is unlikely to be a candidate for embedded non-volatile memory, Reita said: “We decided some time ago there was no way to put [charge] trap-storage memories into 28nm. So we are working on resistive RAM and magnetic RAMs. We are looking at all the three types of resistive RAM at the moment before making a final choice.”

Teepe said the focus at GlobalFoundries for a 28nm-compatible non-volatile memory is on magnetic RAM, pointing to the trend to put an increasing number of important components into the metal stack, such as capacitors.

One Response to Charting out the roadmap for FD-SOI

  1. Pingback: IoT and RF ‘to drive FD-SOI adoption’

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