The road to 7nm sees patterning multiply

By Chris Edwards |  No Comments  |  Posted: June 18, 2015
Topics/Categories: Blog - EDA  |  Tags: , , , , ,  | Organizations: , ,

In a presentation at DAC 2015 in San Francisco, University of Texas lithography researcher Professor David Pan sought to answer the question: when it comes to multipatterning are we ready for 10nm and below? The answer was a qualified yes: it will take cooperation between different parts of the implementation flow.

“Can we make it to sub-10nm using multipatterned lithography? I think yes we can if we have to but a lot of things have to do be done,” Pan said, pointing to possible future hybrid lithography techniques such as multipatterning used together with EUV or e-beam and more advanced computational lithography.

Referring to a paper by Lars Liebmann of IBM and colleagues from Cadence Design Systems and IBM in the SPIE Proceedings, which described one possible lithography strategy for a 7nm process, Pan pointed to the number of different approaches to multiple patterning it would use. “The lesson from this: you will not use just one technique.”

The IBM-Cadence evaluation proposed self-aligned quadruple patterning (SAQP) for the fins of the transistors – self-aligned double patterning (SADP) is already widely adopted for fin patterning. It moved to SADP for poly, several stages of litho-etch for tungsten straps and SAQP for the first metal layer.

Overlay issues

In general, the chemically assisted self-aligned processes suffer less from overlay errors, but the design-rule restrictions they impose are problematic for layers that do not lend themselves to 1D shapes. “You could use SADP for some 2D layouts but it imposes a lot of constraints and it’s not easy to generalise it,” Pan said.

Pan described 2D and 3D vector-based mathematical techniques that can perform layer separation and coloring for triple-stage litho-etch (LELELE) and for SAQP – the dot product of vectors used for different colors make it easier to use familiar cost-minimization algorithms.

For routing layers, Pan said forcing the router to perform all the coloring choices is unlikely to be successful. We have to solve the problem at different levels: standard cell, placement, and routing,” he claimed.

Multipatterning is likely to put a lot more emphasis on standard-cell library construction. Pan pointed to problems not just with making cells that can nudge up to each other without causing coloring conflicts but which support the router better.

Color conflicts

“One trend we have seen for 14nm and 10nm is that because routing has become so complicated and increasingly unidirectional, foundries have introduced middle-of-line [MOL] layers. These can have interactions between cells in a layer and between adjacent rows. During standard-cell design stage you want to minimise such conflicts and make your cell library more robust to multi patterning.

Pan highlighted the issue of pin access, which he said: “is becoming more and more challenging. Your pin shape now is pretty strange so that it can have several access points. When accessing the pin from metal 2, the router’s task is for each of the pins find the right hit points. If you use certain hit points you might break others. We have introduced some optimizations, called Pico, to increase the number of [usable] hit-point combinations to give you more flexibility at routing stage.”

However, the local interconnect used to maximize hit points can create long traces that need to be color compatible with neighbors. Pan proposed using multiple candidate cells that are precolored and which exploit cell assymmetry, with the placer rotating and flipping them to alter the color sequencing in the hope that they result in a valid combination. If that fails, the placer may simply have to shift the cell to another row.

Merging cells could also prove useful in reducing area and coloring conflicts, with the placer allocating a single more complex cell in place of two cells assigned by the synthesis tool.

Pan argued that routing algorithms have to change to cope with multipatterning, moving away from traditional ‘greedy’ algorithms and which attempt to look ahead to find potential coloring conflicts. He said there is an urgent need for fast colorability checkers that make it easier to spot unresolved conflicts so they can be fixed either manually or automatically during the post-layout stages.

Process variations

Because of the likely variance in multipatterning approaches – for 10nm Samsung has indicated that it will use an approach based on LELELE for lower metal layers to improve routability whereas TSMC appears to favor SADP – algorithms will need to cope with the differences, Pan said, particularly for the stitching that is possible under LELELE. “We need algorithms that can cope with different design rules. Set some weights based on your requirements so you can, for example, set off the overlay requirements against [the freedom to perform] stitching.

“Even for SADP there are still some overlay effects: how can we holistically consider overlay?”

A further issue with the more-complex self-aligned lithography techniques is that they do not cater well for mixed metal widths, making it harder to implement double-width wires for power in the lower metal layers. Although there are ways to implement these wider wires, they increase overall area usage.

The possible use of e-beam and directed self-assembly (DSA) with multipatterning to increase the number and variety of shapes that are possible could be important in future nodes, Pan said, but there is an open questions on how to “optimize the number of cut masks or e-beam shots.”

The answer in the short, Pan said, is to: “Push design-technology co-optimization to the extreme. Then hopefully, EUV, DSA, and e-beam will make it into the mainstream.”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors