DVCon Europe: UVM-SystemC backers ready first draft

By Paul Dempsey |  No Comments  |  Posted: November 12, 2015
Topics/Categories: Commentary, Conferences, Blog - EDA, Embedded, - ESL/SystemC, Verification  |  Tags: , ,  | Organizations: , , , , , , ,

The European consortium behind a SystemC version of the UVM verification methodology will deliver a first draft of the standard in the next few weeks. But the project still needs to secure deeper involvement from major vendors.

The initial draft is based on UVM 1.1 rather than the latest 1.2 version, with updates to that nevertheless under way. There is also further work needed on, for example, the Register Abstraction Level and the broader proof-of-concept implementation.

DVCon Europe heard that a Language Reference Manual has now been internally reviewed and is ready to go out for wider comment via the Accellera standards development process.

As of today, only one ‘Big 3’ vendor has been an active participant in UVM-SystemC’s development, Cadence Design Systems.

The good news for the proposed bridge standard is that verification is moving in its direction. UVM-SystemC is intended to move verification up to the system level within a structured environment, while also enabling more re-use throughout the flow. A key driver for this today is the growing use of virtual platforms and virtual prototypes. “The verification environment [for these] is currently ad hoc and not well architected,” UVM-SystemC’s proponents argue.

In the days before UVM brought the verification methodologies of the three largest vendors – Cadence, Mentor Graphics and Synopsys – under the same umbrella, each offered a SystemC verification methodology. However, the combination of UVM with System Verilog has pushed SystemC aside, although some limited proprietary bridges have been available.

The work on UVM-SystemC has been led by NXP Semiconductors, Infineon Technologies, Fraunhofer IIS, Magillem, Continental and UPMC. Their efforts began in 2011. The library they have developed so far includes:

  • UVM components based on SystemC modules
  • A TLM communication API based on SystemC
  • Phases of elaboration and simulation aligned with SystemC
  • Packing/Unpacking using stream operators
  • Template classes to assign RES/RSP types
  • Standard C++ container classes for data storage and retrieval
  • Other C++ benefits (exception handling, multiple inheritance, etc.)

The proposed standard uses a code generator based on that already developed by Doulos for System Verilog. It addresses 11 of the main UVM object and file cases.

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