hardware accelerator

The program for the 58th Design Automation Conference, which returns to a physical format in December, is online and is running its I Love DAC promotion for free access until the end of this month.

Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.

After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.

The latest major release of the EMB2 multicore library introduces C++ wrappers, plugins for GPU programming, and a variety of design patterns

ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.

Achronix has decided to offer the FPGA technology it has developed as a set of embeddable cores.

Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional processors with specialized accelerators.