In an environment where the nanometers keep falling off the node names but the transistors are not getting that much smaller you need to take scaling improvements where you can find them. Imec proposed several years ago rotating the preferred routing directions for the bottom metal layers as one way to eke out a density improvement without making changes to the core spacing of transistors and metal wires and has provided more details on how to do it at this year’s IEDM.
Imec presented a semi-damascene integration approach for implementing the vertical-horizontal-vertical (VHV) layout for the lower metal layers when contacting standard cells in place of a traditional layout where the layer closest to the silicon surface is horizontal, and with an extra layer of MOL traces.
“The VHV routing scheme is a critical scaling booster to enable cell boundaries at the A10, A7, A5, and A3 technology nodes,” said Zsolt Tőkei, program director for nano-interconnects and fellow at Imec. “It is also applicable to future device architectures such as nanosheet, forksheet, and CFET. By extending semi-damascene from the BEOL towards the MOL, we have now also found a way to integrate this promising booster. More detailed investigations will however be needed and for that purpose, Imec is taping out a new dedicated mask.”
The approach makes it possible to implement cells with just four tracks and with a tip-to-tip gap of just 8nm between MOL traces, taking advantage of the self-alignment property of the manufacturing scheme, which is similar to the pitch-splitting that was used for years in double-patterning lithography. According to Imec, the combination of techniques provides a 21% area gain over five-track HVH layouts.
The self-alignment technique was crucial in providing a tight tip-to-tip spacing adjacent lines on the new M0B MOL layer, where two vias (VintB) face each other. The process allows better-defined via edges. The MOL construction process involves two levels of semi-damascene deposition together with a direct metal etch step:
“Roughly speaking, we start from conventionally defined continuous lines and wider vias and, once two metal layers are finished, we split them into two, using the top 16-18nm pitch Mint layer as a hard mask for the final patterning step. This results in three edges, of Mint, VintB and M0B, that are simultaneously self-aligned. With our ruthenium-based two-level test vehicle, we obtained as such an average [critical dimension for vias] of 10.5nm and [an M0B tip-to-tip measurement] as tight as 8.9nm – a key achievement,” said Tőkei.