User2User Silicon Valley is two weeks away

By TDF Editor |  No Comments  |  Posted: April 18, 2019
Topics/Categories: Conferences, Design to Silicon, Blog - EDA, - HLS, Blog - PCB, - RTL, Tested Component to System, Verification  |  Tags:  | Organizations: , , , , , , , , ,

Registration is open for the 2019 Silicon Valley edition of Mentor’s User2User conference and exhibition in just a fortnight’s time, on Thursday May 2, 2019 at the Marriott Hotel in Santa Clara, California.

The all-day event features three keynotes and a range of technical presentations across six areas featuring more than 45 papers.

Program strands this year include DFT with extra reference to semiconductor data analytics, and MEMS and analog/custom design with a focus on the Internet of Things. Others address analog/mixed-signal verification, functional verification and emulation, IC design and verification, and high density advanced packaging.

User papers will be presented by engineers from companies such as Cypress Semiconductor, Invensense, Microsoft, Qualcomm, SKHynix and Wave Computing (Wave’s use of Mentor’s tools to develop its AI technology is also discussed here)

User2User continues to be free-of-charge, including on-site parking, lunch and a networking reception to conclude the day. There is also an exhibition and expert Mentor staff will be on hand at the U2U Exchange to discuss the company’s full range of tools and solutions with attendees. This year’s exhibitors include Arm, GlobalFoundries, Samsung, TowerJazz, TSMC, and Oski Technology.

Registration is now open and full details of U2U Silicon Valley can also be found at this link. Meanwhile, here are some of the highlights.

Keynote User2User speakers

  • Joe Sawicki, Executive Vice President, Mentor IC EDA
  • Vicki Mitchell, Vice President, Technology Services Group, IPG, Arm
  • Allen Sansano, Vice President Engineering, Wave Computing

Selected User2User Silicon Valley presentations


  • Accelerating AR/VR Computer Vision Algorithms in a Hybrid HLS/RTL Approach – Facebook
  • In Depth Power Optimizations of Ultra Low Power STM32 Microcontroller with Nitro-SoC –STMicroelectronics
  • Close Coverage 10X Faster Using Questa inFact – Microsoft
  • Integrated Approach to Power Domain/Clock Domain Crossing Checks – Challenges and Implementation – Cypress Semiconductor
  • Analog/Mixed-Signal (AMS) Design Challenges for High Speed SerDes in nm-scale CMOS for 5G and Automotive Applications – Qualcomm
  • Accelerating Verification of High Precision MEMS Sensor SoCs with Symphony – Invensense
  • Parasitic Extraction for GlobalFoundries 22FDX-EXT PDK – GlobalFoundries
  • Maximizing Veloce Value for AI Design Verification – WAVE Computing
  • SSD Controller Verification with Veloce Solutions – SK Hynix Memory Solutions
  • What’s Driving Heterogeneous Integration and Which Packaging Option is Best? – TechSearch International
  • Package Assembly Design Kits Bring Value to Semiconductor Designs – Amkor
  • Improving Test and Fault Coverage with Tessent Cell-Aware Models using Artisan Physical IP Library – Arm
  • An AI Chip DFT Design Flow for Catching Time-To-Market – Gyrfalcon Technology Inc.
  • A Case Study of Testing Strategy for AI SoC (Enflame) – Mentor
  • GlobalFoundries 22FDX Custom Design with Mentor Tanner Tools – GlobalFoundries
  • Supersede 5G – Gain ICs

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