Fusion improves timing say Synopsys users

By Chris Edwards |  No Comments  |  Posted: July 3, 2018
Topics/Categories: Blog - EDA  |  Tags: , , , , ,  | Organizations: , , , ,

At its SNUG conference in March, Synopsys publicly unveiled its Fusion portfolio and data model, a way of combining many different tools to deal with nanometer design problems. Early-access customers talked about their experiences with the suite in a panel session at the Design Automation Conference (DAC) in San Francisco last week (June 25, 2018).

Synopsys introduced the Fusion technology to enable tools such as IC Compiler II (ICC II), Design Compiler Graphical (DCG), PrimeTime, StarRC, IC Validator, DFTMAX, SpyGlass, and Formality equivalence checking to share information about a design. The Fusion technology comes in a variety of forms: Design Fusion; ECO Fusion; Signoff Fusion; and Test Fusion, each aimed at different parts of the flow. ECO Fusion, for example, enables the rapid insertion of changes at the physical level by using optimizations at different layers. Implementation tools can perform logic restructuring to improve area and timing that can span blocks and test structures. According to Synopsys, the use of a common data model enables the same interpretation of rules and design intent throughout the flow, and is based on a shared massively parallel and machine-learning ready infrastructure.

Power and area targets

Kazuhiro Takahashi, senior principal engineer at Renesas, said the company has been working closely with Synopsys since 2000, becoming an early adopter of DCG and then ICC II. “Renesas was one of the first to use ICC II,” he said.

Takahashi said the traditional flow of synthesis to place and route and finally signoff is running out of steam – optimizations performed in isolation by each tool do not maximize performance or area. “We need tighter integration of synthesis and layout and we think we can do this with the Design Fusion flow. We expect better QoR [quality of results] especially at the chip level,” he said.

On one project, a 400MHz automotive microcontroller with stringent area and leakage power targets, Takahashi said work with the new type of flow achieved an area reduction of 8 per cent and a leakage reduction of 15 per cent compared to a traditional approach.

Sorin Dobre, senior director of technology at Qualcomm, said his company is working closely with Samsung to bring products based on a 7nm process to market and to migrate quickly to denser derivatives from next year. “We are moving fast to have high-volume production in 4nm and 5nm,” he said. “We are using Synopsys tools and flow in 7nm and on the previous technologies. Why Fusion? Our target is for improvement in the quality of design, a reduction in power and a reduction in the time to tapeout. We see Fusion as an enabling platform moving forward.”

Cutting slack

Dobre said evaluations of the most recent tools on block-level designs saw large reductions in negative slack and negative hold slack. “We are able to converge the design significantly faster using timing analysis that is physically aware. We are working with Synopsys to enable this not just for the most advanced technologies but other nodes, such as 11nm and 22nm.”

Qualcomm has also made use of the integration between ICC II and Ansys RedHawk. “To speed up physical design convergence we are looking to enable technologies for integration inside Fusion, to take into consideration the effects of IR drop on timing. When you go to lower technology nodes and the lower voltages they enable, designs become very sensitive to unexpected voltage drops.”

Saran Kumar Seethapathi, principal IC design engineer at Broadcom, described how one part of his company has moved from using RedHawk as a standalone tool to integrating it into the Fusion-based flow. The group is an Arm centre of excellence. “We deliver hard macros for the various system groups. We do these Arm cores in a semicustom fashion on timescales of three to eight months. We are doing these very high speed cores in a very tight schedule.”

Seethapathi said the team was keen to obtain identical IR-drop analysis results from the RedHawk tool in the new flow. “And they were,” he said. In use, the integrated use of the tools led to a 10 to 15 per cent improvement in static and dynamic IR drop.

High-performance design

Philip Steinke, senior manager of CAD and physical design at AMD also had high performance in mind in his company’s use of the Synopsys flow: “We believe high-performance computing is the heart of the next generation of computing. It’s what’s driving growth in our industry.”

AMD used DCG and ICC II on its Ryzen 7 project, a design with four CPUs and ten graphics cores and a total of 4.5bn transistors. “It had lots of physical reuse and a lot of congestion. With these kinds of challenges we are constantly looking for tool and methodology improvements to stay ahead.”

In recent years, AMD has applied POCV, multibit register banking and global-route layer binning to optimize the physical design. “Even with that, at the latest process nodes the challenges get harder. We need the tools to anticipate more,” Steinke said. “We started out looking at Fusion for design resynthesis. And we also brought in the Signoff Fusion.”

The synthesis transforms that become available in place and route through the Fusion flow help optimize elements like test logic that will be incorporated after conventional synthesis. “The logic restructuring algos can see all that,” Steinke said. “We tested this on some cutting-edge GPU blocks and saw an average 2.5 per cent area reduction and an average 18 per cent improvement in TNS.

“The third feature we are taking advantage of is PrimeTime delay calculation in Fusion on the final pass of routing, rather than having to feed that back in afterwards. It catches those final outlier paths that would normally be problematic. We saved about a week per tile.”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors