Toward easier, faster test pattern simulation
Validating test patterns is a notoriously tricky and laborious process. Mentor Graphics has some new ideas on that front.
Tested Component to System
User2User preview: Silicon Valley edition rolls out this month
Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
IP implementation variety drives latest partnerships
Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
Mentor builds out verification IP for memory
About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
Mentor’s Veloce boasts emulation gains fueled by software
Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
Three key ways to reduce silicon test costs
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Samsung taps Mentor tools for higher yielding close-loop DFM
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
From Darwin to Mao: how multi-patterning could move up the flow
Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
Mentor’s Wally Rhines on tools as a cultural issue
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
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