Mentor Graphics has made a clutch of software-based enhancements to its Veloce emulation system that, the company says, offer significant boosts in performance and functionality. The upgrades unveiled today (February 25) cover the core Veloce OS3 operating system and further build out Mentor’s family of task-specific Veloce Apps.
The improvements to OS3, shared by all existing and potential Veloce customers, cut RTL and gate-level compile times while speeding the delivery of waveforms for use in debug by 2X.
The new Veloce Apps address projects where some traditional in-circuit emulation (ICE) is necessary, the validation of testcases before tape-out, and emulation run-time reductions for complex multi-clock SoC designs. Customers buy Apps as appropriate to their projects.
The latest innovations come ahead of any formal announcement about moving the Veloce family to a new generation of custom IC.
“We are working on new silicon and will be talking about that ‘soon,’” said Gabriele Pulini, product marketing manager in the Mentor Emulation Division. “But the priority is set by Veloce’s ability to have the capacity for today’s designs, and maintain and improve performance with new features like these.”
Veloce is powered by the Crystal 2 custom chip. These are stacked in high-performance boards across a range of emulators with capacities from 250 million gates (the entry-level Quattro) to 2 billion gates (the top-of-the-range Double Maximus).
Upgraded Veloce OS3
RTL compile time
Mentor has collaborated with workstation and server partners at HP and Dell to develop optimized configurations for RTL compilation of designs prior to their installation on Veloce. These leverage high-performance computing techniques. Mentor says that the result is an average 2X improvement on time-to-RTL-compile. Pulini added that the research has given it a better ability to advise customers on how to construct the most efficient compilation environments, alongside their emulators.
Gate-level compile time
“More and more customers are now using emulation at the gate-level, post synthesis, as it provides the closest representation of the design and therefore provides greater confidence in silicon fidelity,” said Pulini. As a result, the Veloce OS3 flow here has also been optimized, to offer performance advantages such as a 5X acceleration in run-time and – given the flat and hierarchical nature of gate-level compilations – a much smaller memory footprint.
Time to waveform
The availability of waveforms to enable earlier debug – Mentor uses the term ‘time-to-visibility’ – has been addressed by two sets of enhancements. In addition to upgrades within Veloce OS3 itself, the company has also improved the hardware interfaces to workstations. Within the typical flow (test runs/raw waveforms/constructed waveforms/waveform viewing), Mentor says the new features deliver a 2X increase in speed.
New Veloce Apps
Where the Veloce OS3 compile enhancements largely address stages between the workstation and the emulator, the new FastPath app optimizes run-times within the emulator itself. For large designs with many clocks, it identifies features that typically limit the emulator’s efficiency and compensates as appropriate. The typical gain, Pulini said, is a 50% reduction in run-time.
In parallel with customers’ increasing use of gate-level emulation, there has also been a drive to extract greater efficiency for pre-validating testcases on the emulator. The goal is to get as close to a pre-prepared production test scenario as possible before tape-out. Results for the DFT App in beta across three types of design showed that it could reduce validation times by anything from 1,000X to 4,000X against simulation.
Pulini said that the app’s approach also makes it easier for users to swap different test vectors in and out of the emulator for validation, thanks to the division between the STIL file at the workstation and the DUT housed on Veloce itself, as well as innovation in the transactor between the two.
In-circuit emulation – the attachment of external physical devices to an emulator – is increasingly unloved, particularly as companies seek to locate emulators in data centers rather than labs.
However for some designs – notably in telecoms and markets sensitive to design-for-security concerns – it is still an necessary part of verification. The Deterministic ICE app aims therefore to offer a best-of-both-worlds.
An initial ICE run will use a connection to an external physical device (e.g., PCIe hardware) and is captured cycle-to-cycle. Using the app, a record of this ICE run is placed in a replayable database. It can then be used virtually and repeatedly for debug.
Mentor sees the app being used in areas such as power optimization and hardware/software co-verification. Also, given the trend to data center virtualization, access to results from the initial ICE run can more easily be shared, reviewed and debugged across an enterprise rather than chiefly where the emulator is installed.
One further benefit, Pulini said, is that Deterministic ICE allows engineers to more easily focus on issues that can arise on different cycles in a pure ICE exercise with multiple runs, making them harder to detect. On the virtual replay, the issue will always be at the same cycle as the original run.
The fourth age of emulation
The new Veloce Apps join six already available for Power; Coverage/Assertions; Software Debug; Peripheral Solutions; Visualiztion and Enterprise Server access.
Pulini concluded that emulation is now entering its ‘fourth age’, one where the hardware on the product alone is “no longer the differentiating factor”. Software Apps now allow for the use of emulators across a much broader set of use cases and in turn customers require further tailored ways to mitigate design risk.
This is reflected in the evolution of Mentor’s own emulation R&D team, Pulini noted. Of the 400 engineers on that team today, the vast majority are working on software while just 80 are attached to hardware.
In other words, expect more Veloce Apps in the none-too-distant future.