Tested Component to System

May 13, 2014

Mentor targets 10X cut in reliability test for power electronics

New MicReD power tester identifies failure causes without the need for post-test lab analysis
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November 4, 2013

Amkor keeps question mark next to ‘full’ 3D-IC in 2016

Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
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April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
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June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
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June 16, 2011

RS-DIMM rugged memory becomes XR-DIMM

We’ve just heard from the Small Form Factor Special Interest Group (SFF-SIG) that the RS-DIMM rugged embedded memory featured in the latest print edition of Tech Design Forum and online has been renamed XR-DIMM (eXtreme Rugged Dual In-Line Memory Module) with immediate effect. Paul Rosenfeld, SFF-SIG’s president, says the change is intended to “reflect the […]

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May 10, 2011

NABshow Silicon

Wearing another hat, I recently got back from NABshow, the huge broadcast engineering event in Las Vegas. As a self-confessed movie buff, I enjoy it more than CES. Smaller crowds, too. Only about 90,000.

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