yield


March 27, 2020

Tackling IR drop and EM with a push-button via utlility

Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
Article  |  Topics: Digital/analog implementation, Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 10, 2016

DFT to expand its role for long-term yield

Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
June 1, 2016

Samsung taps Mentor for Closed-Loop DFM

Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
October 6, 2015

Samsung taps Mentor tools for higher yielding close-loop DFM

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
June 7, 2015

DAC 2015 forecast: Cloudy with a chance of Spice installs

Spice regressions, library characterisation and yield analysis are all being promoted as suitable for running on the cloud
Article  |  Topics: Verification  |  Tags: , , , ,   |  Organizations: ,
June 4, 2012

DAC 2012: Google your way to DFM

The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
Article  |  Topics: Design to Silicon, Standards  |  Tags: , , , ,   |  Organizations: ,

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