Design to Silicon

Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.

DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.

STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.

The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.