optimisation


December 19, 2016

White paper discusses optimising the efficiency of DDR memory subsystems

DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
Article  |  Topics: Design to Silicon, Blog - IP  |  Tags: , ,   |  Organizations:
May 19, 2015

eSilicon offers ‘no gain, no pain’ ASIC block optimisation service

Design and manufacturing services company draws on big data to offer ASIC block optimisations
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: ,   |  Organizations:
February 7, 2014

Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%

Uses improved logic optimisations and a new approach to meeting timing.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors