Creating a reference design flow for 10nm processes: video

By Luke Collins |  No Comments  |  Posted: August 27, 2016
Topics/Categories: Conferences, Design to Silicon, Blog - EDA  |  Tags: , ,  | Organizations: ,

Increasing process complexity and lithographic challenges are likely to see the semiconductor industry use the 10nm node for a long time, so how do you build an efficient design flow to get the most out of it?

Synopsys has posted a video of a breakfast meeting at DAC during which its collaboration with Samsung Semiconductor to build a design flow for the upcoming 10nm flow was discussed.

In the video, Kelvin Low, senior director of foundry marketing, Samsung Semiconductor, discusses progress on his company’s processes.

Samsung Semiconductor has already shipped more than half a million finFET wafers at 14nm, and is now working on its 10nm process offering. Low expects that shifting from the 14fF process to the upcoming 10nm process will offer the same 30% performance gain experienced in the shift from Samsung’s 28LPP to 14LPE processes. Progress beyond this point is unclear.

“Foundries are pushing immersion lithography beyond 10nm and we see this as very high risk,” said Low, adding that he believed that a 7nm node that did not use EUV lithography would be short-lived.

At 10nm, Samsung has already done risk production on its 10LPE process, and hopes to see it in mass production by the end of the year. A PDK, libraries, IP and design flows are available for the process.

A follow-on 10LPP process is in development, which should offer a 10% performance bump over 10LPE and enter risk production by the end of the year.

An early PDK and library for this process is already available.

“We view 10nm as a healthy and long-lived node,” said Low.

JC Lin, vice president of IC Compiler II R&D, Synopsys, outlined some of the challenges of developing tool support for these advanced nodes.

These include achieving high yields with increasing density, coping with rising wire resistance, and supporting more placement and routing rules, for example to ensure that when pins get placed on these dense layouts, they can also be routed.

The use of finFETs has also increased the complexity of device modelling, while the placement and routing tools also need to support triple patterning to achieve the required density. Other challenges include building an effective power grid, and managing signal EM issues. All this has to be dealt with in a context in which customers are being increasingly careful about sign-off, often doubling the number of process corners they want to check with a consequent impact on turnaround times.

To address these issues, Synopsys has introduced features into IC Compiler II and related tools including netlist restructuring (adjusting the circuit during placement to make it routable), total negative slack based placemen, local skew optimisation, and concurrent clock and data optimisation to improve clock topologies. ICCII also uses the same timer as in PrimeTime, to ensure better correlation between design and sign-off. There’s also integrated and incremental ECO.

Andy Potemski, senior director of reference flows and Lynx R&D, Synopsys, discussed the foundry reference flow it has built with Samsung Semiconductor for the 10LPE process. The four-stage flow has an automation layer (to manage repetitive tasks) and a technology layer to reflect the details of the process.

“The flow is a balanced starting point that is scalable for a wider variety of applications,” said Potemski, who added that it had been developed using a Cortex A53 CPU design as a ‘pipe cleaner’.

Samsung Semiconductor specified that the design should be done with all the timing at worst-case corners, and targeting a low IR drop. The design should be clean vs DRC and colouring issues, and should use Synopsys’ IC Validator’s PV and POCV timing sign-off strategies.

The flow the team developed included the use of Design Compiler Graphical, particularly for its congestion-driven restructuring and layer-aware optimisation features.

For the design-planning phase, the reference flow was tuned to handle issues such as the insertion of boundary cells and tap cells.

Placement had to be colour aware, and so there had to be a colour ‘legalisation’ step using colour shifting. Colour planning also had to be done for the power-grid and power-grid vias.

Timing variations in these advanced processes are increasingly dependent on slew and load, and this is leading to non-Gaussian timing distributions. The reference flow therefore specified the use of PrimeTime POCV features within ICC Compiler II to address this issue.

Synopsys’ IC Validator tool was specified to handle process hotspot checking and repair, while IC Compiler II and PrimeRail were used to in-design IR drop analysis

Watch the video

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors