How to save money in process development by moving experiments out of the fab and into the computer.
Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.
The semiconductor industry is reaching a crunch point at which companies that form it have to work together much more closely, says Malcolm Penn of Future Horizons.
Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.
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