“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic. So, some design teams are turning to IP that started out as open source to provide more scope for experimentation.
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional processors with specialized accelerators.
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
NXP discusses second silicon flavor for automotive radar, after earlier launch of postage-stamp devices.
Startup launches an analog-circuit migration and optimization tool that uses less simulation time than traditional approaches the company claims.
Menta SAS has launched an embedded FPGA core family that improves density over previous versions.
Concept Engineering is introducing a version of its Nlview family of automatic schematic generation products that runs inside a standard web browser.
Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.
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