BSIM Compact Model

April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.

Article | Topics: Commentary, Conferences, Design to Silicon, Blog - EDA, - Standards | Tags: 10nm, 7nm, BSIM Compact Model, FD-SOI, finFET, post-Moore, R&D funding, SPICE | Organizations: GlobalFoundries, IEDM, Intel, Silvaco, SNUG Silicon Valley, Synopsys, TSMC, UC Berkeley