Design to Silicon

October 11, 2013

India outlines subsidies for foundry fab plan

The Indian government will meet up to a quarter of initial capital costs for a foundry capable of nodes up to 45nm and 40,000 wafer starts per month at 300mm.
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October 1, 2013

TSMC 16nm finFET, Ge 20nm p-finFET set for IEDM

TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
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June 17, 2013

Synopsys doubles speed of formal ECO checking

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
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May 28, 2013

Fabless, IP designers need process simulation tools, says Coventor CTO

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
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May 22, 2013

Gartner: Multi-patterning here to stay, EUV lithography still 50:50

Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
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April 10, 2013

3D-IC cooling ascends the agenda

US defense research agency DARPA sets targets for cooling overall systems and hot spots in stacked silicon, and backs joint research from Rockwell-Collins and Georgia Tech.
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April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
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April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
March 27, 2013

Intel and ST stake claims to foundry low power designs

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.
December 13, 2012

3D-IC integration prospects improving, say IEDM researchers

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
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