Design to Silicon

November 4, 2013

Amkor keeps question mark next to ‘full’ 3D-IC in 2016

Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
Article  |  Tags: , , , ,   |  Organizations:
October 23, 2013

3D-IC focus for GSA’s Taipei Memory+ event next week

Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
October 11, 2013

India outlines subsidies for foundry fab plan

The Indian government will meet up to a quarter of initial capital costs for a foundry capable of nodes up to 45nm and 40,000 wafer starts per month at 300mm.
Article  |  Tags: , ,   |  Organizations: ,
October 1, 2013

TSMC 16nm finFET, Ge 20nm p-finFET set for IEDM

TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
Article  |  Tags: , , , , ,   |  Organizations: ,
June 17, 2013

Synopsys doubles speed of formal ECO checking

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Article  |  Tags: ,   |  Organizations: ,
May 28, 2013

Fabless, IP designers need process simulation tools, says Coventor CTO

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
Article  |  Tags: , , ,   |  Organizations:
May 22, 2013

Gartner: Multi-patterning here to stay, EUV lithography still 50:50

Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
Article  |  Tags: , , , ,   |  Organizations:
April 10, 2013

3D-IC cooling ascends the agenda

US defense research agency DARPA sets targets for cooling overall systems and hot spots in stacked silicon, and backs joint research from Rockwell-Collins and Georgia Tech.
Article  |  Tags: ,   |  Organizations: , ,
April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
Article  |  Tags: , , , , ,   |  Organizations:
April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors