The Indian government will meet up to a quarter of initial capital costs for a foundry capable of nodes up to 45nm and 40,000 wafer starts per month at 300mm.
TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
US defense research agency DARPA sets targets for cooling overall systems and hot spots in stacked silicon, and backs joint research from Rockwell-Collins and Georgia Tech.
The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
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