Design to Silicon

July 9, 2015

IBM and friends at 7nm: breakthrough or science project?

IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
June 4, 2015

COMPUTEX 2015: Taiwan and mainland China face off in IoT platforms

It wasn't just ARM and TSMC that launched a 55nm IoT platform this week. Across the Taiwan Strait, Brite and SMIC have unveiled a similar offering. The competition could tell us a lot about the IoT market's future.
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May 19, 2015

eSilicon offers ‘no gain, no pain’ ASIC block optimisation service

Design and manufacturing services company draws on big data to offer ASIC block optimisations
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December 18, 2014

Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL

The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
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November 12, 2014

Chip tariff eliminated and the big winner is… China?

Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
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November 4, 2014

From Darwin to Mao: how multi-patterning could move up the flow

Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
October 28, 2014

imec and Coventor partner for 7nm process development

Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
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September 11, 2014

TSMC: e-beam winning on cost over EUV for lithography

EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.
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June 6, 2014

eSilicon to cut costs of ASIC development for IoT, other markets

Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
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June 5, 2014

Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond

Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore's law scaling
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