10nm flow reveals complexity of finFET design process
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Design to Silicon
IBM and friends at 7nm: breakthrough or science project?
IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
COMPUTEX 2015: Taiwan and mainland China face off in IoT platforms
It wasn't just ARM and TSMC that launched a 55nm IoT platform this week. Across the Taiwan Strait, Brite and SMIC have unveiled a similar offering. The competition could tell us a lot about the IoT market's future.
eSilicon offers ‘no gain, no pain’ ASIC block optimisation service
Design and manufacturing services company draws on big data to offer ASIC block optimisations
Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
Chip tariff eliminated and the big winner is… China?
Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
From Darwin to Mao: how multi-patterning could move up the flow
Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
imec and Coventor partner for 7nm process development
Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
TSMC: e-beam winning on cost over EUV for lithography
EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.
eSilicon to cut costs of ASIC development for IoT, other markets
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
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