parallel processing


February 1, 2017

Five steps to faster FPGA implementation

Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
Article  |  Topics: Design to Silicon  |  Tags: , ,   |  Organizations:
July 12, 2016

Synopsys speeds ATPG, adds ISO 26262 certification

Synopsys has introduced TetraMAX II, a faster and more parallelisable ATPG and diagnostics solution, which is now also certified for use in ISO 26262 compliant automotive designs.
June 3, 2015

Cadence deploys parallel strategy for faster synthesis

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.
March 22, 2013

DATE: ARM proposes ‘unit of compute’ as basis for energy-efficient systems

ARM CPU chief proposes 'unit of compute' as building block for energy-efficient computation systems
Article  |  Topics: Conferences, Blog - Embedded  |  Tags: , , , , , , , , ,   |  Organizations:
March 12, 2013

EDA sets sail in a ‘sea of processors’

The purchase of Tensilica by Cadence Design Systems could prove the way that EDA and multicore-based system design come together.
February 23, 2013

Parallel API for embedded systems goes public

The Multicore Association has published the MTAPI specification for a programming interface that aims to simplify the job of building applications that can not only use many cores running in parallel but schedule jobs dynamically depending on which types of core are available.
Article  |  Topics: Blog - Embedded  |  Tags: , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors