Speeding up AMS design in the age of finFETs

By Luke Collins |  No Comments  |  Posted: October 10, 2016
Topics/Categories: Conferences, Design to Silicon  |  Tags: , , ,  | Organizations: ,

How do you accelerate the design of analogue and mixed-signal (AMS) standard cells, memories, IP and SoCs? Speakers from ST Microelectronics, GSI Technology, Samsung and Synopsys’ MS IP group, spoke at a lunch hosted by Antun Domic, executive vice president and general manager of the Design Group at Synopsys, about how they were using the company’s latest AMS design tool, Custom Compiler, to address this issue.

Domic opened by describing Custom Compiler’s approach, which moves away from trying to apply digital design techniques, such as textual constraints files, to AMS design. This, he argued, results in a ‘take it or leave it’ approach to outcomes. Custom Compiler, instead, uses what Domic called visually assisted automation, to enable designers to work using successive refinement, fixing the blocks that they are happy with and then focusing on those that need further work. There’s also automation through layout assistants, templates and pattern reuse, and the integration of assistants that can run DRC, EM and IR drop, and RC checks earlier in the flow, rather than as an ‘after the fact’ check once the design is finalised. 

Early EM checks

Atul Bhargava, a senior staff engineer at STMicroelectronics, discussed how his company was introducing Custom Compiler for its library and IP development. 

He noted that an internal survey showed that AMS designers at the company were spending 30% of their time on placement, 25% on routing and 45% on validation, including checking issues such as DRC/LVS, EM, IR drop and other issues that affect reliability. In the company’s previous flow, EM and IR checks happened at the last stage of the design. If there was a scheduling issue, the time for these checks could be reduced, leading to the prospect of reduced reliability. With Custom Compiler, EM checks can be brought forward in the flow to the point at which the schematics are done, making it easier to check reliability.

Bhargava also discussed the ‘search and replace’ function in the tool, which can search and replace not only on a design’s devices and nets, but on properties too. This makes it easier to move a design between process technologies, or to update it when a preliminary PDK gets a new release. The tool is now in use by ST’s SRAM and standard-cell development teams.

Matched-length net routing for performance

Randy You, CAD manager, GSI Technology, talked about some of his company’s challenges in designing high-performance memories, and their choice of Custom Compiler to undertake a design on a 16nm process.

The first challenge is responding to the increased complexity of design rules: You said his team faced working with three times as many rules at 16nm as it did at 40nm. In its previous flow, when designers were editing layouts and placing blocks, they would then have to manually measure the distance to adjacent blocks to ensure there were no violations. Custom Compiler’s design-rule driven approach dynamically displays the distances between objects, and is also aware of potential double-patterning issues.

Custom Compiler also has a feature called Quick DRC, which runs DRC checks on the currently active layout layer and within the currently displayed window only, for fast checking during design, although a full DRC run is still necessary eventually.

For EM analysis, You said his team’s previous approach involved doing the layout, extracting the resistance of the power nets, running a current density check on them and then fixing any violations through redesign. Custom Complier can back-annotate currents into the layout after circuit simulation, so that you can then do check for EM and IR drop issues. The analysis includes recommendations for adjusting metal width and/or device resizing.

You’s third key design issue is being able to route balanced pairs of nets with equal lengths. In their previous flow, designers were doing placement, running routing, checking the length and resistance of the resultant nets and then adjusting as necessary. Custom Compiler can automatically do matched-length routing to handle the issue.

Samsung and Synopsys add finFET smarts to PDKs

Bonhyuck Koo, principal engineer in the design services team at Samsung Electronics, talked about how his company was enabling its customers to use Custom Compiler to design on its advanced foundry processes. He picked out three key challenges of working with its 14nm finFET process: creating a finFET-aware design flow, dealing with multipatterning constraints, and handling design rule complexity.

Samsung and Synopsys have worked together to create a certified flow for the 14nm process that combines Custom Compiler with what Samsung calls an iPDK. Together they have been able to embed solutions to each of these issues in the flow.

The tool and PDK now support a finFET-aware approach to design, with automatic fin-grid snapping, support for exploring issues to do with device abutment, and an editable way to define guarding areas. To address double-patterning issues, the tool is color-aware for features such as Pcells, metal lines, and vias, and can do automated or net-based coloring. The flow also supports density checks on individual colors.

To counter the growth in design rule complexity, Custom Compiler supports design-rule driven design, early EM checking, and a parasitic-aware approach. Errors are reported automatically and the flow offers automatic fixes. Samsung is now working on an iPDK for its 10nm process.

Keeping up with evolving processes

Phil Morris, an engineer in Synopsys’ MS IP group, talked about the work his group has done with the Synopsys tool development team to address issues he and his colleague face in developing advanced MS IP blocks for multiple, rapidly evolving advanced processes – for example, having to tune a block’s design to match both the LPE and LPP variants of Samsung’s 14nm process.

He pointed out that finFET-based design means having to balance contradicting demands: for example, making wires fatter will reduce their resistance, which is good for EM issues, but the additional capacitance will undermine the design’s performance and density. Small changes in a design, for example to fix an EM issue, can be very disruptive, “so you can’t lay out an inverter without an EM analysis”.

Other issues that have to be addressed during design are achieving the right ratio of routing densities on different coloured metal routing layers, dealing with device-spacing issues which can constraint poly density, and the fact that the pitch at which fins are placed may be different from the metal pitch, so you can end up with some devices laid out in rows that can’t be connected in the same way as other devices.

Synopsys also has the particular challenge of being expected to have IP ready for use with new processes as soon as they are released, and so has to work with the earliest versions of a process, and quickly migrate its designs each time it is updated.

For the upcoming 10nm processes, Synopsys created a taskforce including Custom Compiler developers, R&D and the IP designers, so they could share a common view of what the issues are and how best to address them. This led to the creation of facilities such as template-driven design, which can give DRC-clean layouts of common architectures; track-based placement strategies that enable designers to focus on getting the metal layers right first, with the devices then moving into place below them; and a symbolic editor for device placement.

Other features include a track and via planner, to speed up routing; layout editing assistants that can automatically take cell designs and wrap them in a guard ring with tap cells; and the EM assistant mentioned by other speakers.

The lunch was held at this year’s Design Automation Conference, in Austin, Texas. To view the video, click here.

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