Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond
Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore's law scaling
Design to Silicon
Samsung certifies Synopsys tools, IP at 14nm
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Mentor’s Wally Rhines on tools as a cultural issue
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
Intel and Altera extend foundry deal into interposer and full 3D
Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.
TSMC hints at glass interposer for mobile SoCs
Glass may be the high frequency interposer option given silicon concerns about power and noise. TSMC adds another pathfinder to its 3D arsenal.
Qualcomm’s take on preserving Moore’s Law economics
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
FinFETs’ III-V future promises sub-7nm, RF and opto CMOS
FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
TSMC succession plan emphasizes stability
TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
TSMC demonstrates readiness for 3D-IC
Research projects to verify methodologies, address third-party integration challenges and add a low-cost interposer-like technology to the 3D-IC family make their mark.
Amkor keeps question mark next to ‘full’ 3D-IC in 2016
Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
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