The circuits sessions at mid-June’s VLSI Symposia in Honolulu will feature a number of papers that push the performance of scaled mixed-signal processes. They include a integrated 112Gb/s PAM4 receiver on a 16nm finFET process and a self-calibrating ADC that boosts linearity by more than 30dB.
The leading vendors of programmable-logic devices have embraced PAM4 signaling as a way to speed up communication between ICs. On a 16nm finFET process, engineers from Xilinx claim to have increased performance to 112Gb/s on their receiver design with the help of a 64-way interleaved successive-approximation ADC. A combination of peaked-follower buffering, multirank sampling, and timing-skew calibration lets the ADC sample at up to 56GS/s. The receiver consumes 590mW and achieves a bit-error rate of 2×10-5 without forward error correction over a channel with 20dB loss.
Analog Devices has employed background calibration on an ADC design for a 40nm CMOS process that improves AC linearity by more than 30dB to achieve 16bit-level performance. According to the team behind the circuit, the calibration technique works with any input signal and converges within a few milliseconds. The converter design consumes around 100µW at 1MGs/s and offers a spurious-free dynamic response of 100dB.
A collaboration between UC Berkeley and TU Delft has led to the development of a high-linearity, high signal-to-noise ratio headphone driver on a 65nm process. Implemented as a class-AB driver, the circuit uses a 65nm process and is aimed at mobile devices. To overcome typical problems of distortion on CMOS processes, the design focuses on improving output-stage biasing and introduces a novel frequency-compensation scheme. The team claims it improves linearity by more than 12dB and SNR by more than 15dB over previous CMOS designs, while delivering nearly 50 per cent more power to the load.
The conference takes place in at the Hilton Hawaiian Village, Honolulu from June 18 to June 22, 2018.