SAR


June 20, 2018

SAR-VCO combo tunes RF receiver power on 16nm

Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
June 8, 2015

S3 aims at MIMO WiFi with smaller ADC core

S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
Article  |  Topics: Blog - IP  |  Tags: , , , , , ,   |  Organizations:
March 20, 2014

ADC design shifts gears for lower power

SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors