verification coverage

July 2, 2018

Tools suppliers back version 1.0 of portable-stimulus standard

Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.
May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
February 6, 2018

Machine learning and visualization ‘needed for coverage’

Traditional functional coverage has run out of steam and novel methods to improve the understanding of what tests are doing are needed to make progress. That is the view of Greg Smith, director of verification innovation and methodology improvement at Oracle.
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February 1, 2018

Metrics introduces elastic compute to handle peak-time verification

Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
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October 8, 2015

Expanding role of UVM takes center stage at DVCon Europe

Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.
June 8, 2015

Formal integration enhances bug-hunting for Cadence

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
December 11, 2014

Use-cases drive high-level verification tool

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
October 4, 2014

Carbon introduces exchange for building and stressing virtual prototypes

Carbon Design Systems has introduced a web portal to streamline the process of finding the most appropriate executable models for a system-level virtual prototype.
July 8, 2014

Focusing coverage for system-level integration

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
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June 9, 2014

Applications won’t find all the bugs, but they have their uses

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.

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