A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
Traditional functional coverage has run out of steam and novel methods to improve the understanding of what tests are doing are needed to make progress. That is the view of Greg Smith, director of verification innovation and methodology improvement at Oracle.
Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
Carbon Design Systems has introduced a web portal to streamline the process of finding the most appropriate executable models for a system-level virtual prototype.
Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
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