Breker Verification Systems, specialist in test content synthesis solutions for SoC, UVM and post-silicon verification environments, will showcase its latest innovations at this week’s Design Automation Conference (DAC 2021) in San Francisco during the event’s exhibition days (Exhibition: Dec 6-8; Conference Dec 5-9). It can be found at Booth #2528 in Moscone West.
The company will focus on how it has built on its Cache Coherency Test Solution with its next-generation System Coherency Synthesis TrekApp.
The System Coherency Synthesis TrekApp generates thousands of high-coverage tests to stress cross-system coherency for a broad range of SoC platforms and processors. It uses abstract models of common and novel algorithms to automatically generate coherency test content for complex, multi-agent system platforms based on coverage directives.
The TrekApp can be configured for Arm, RISC-V and other processor configurations and a broad range of storage and I/O architectures. It is part of the Breker TrekApp solution library that provides automated test content for a variety of SoC scenarios, including cache coherency, Arm and RISC-V integration, power domain management, security and network traffic generation.
TrekApps operate on the Breker Test Suite Synthesis Solution and Synthesizable VerificationOS for automated, coverage-driven test generation for a variety of multi-threaded platforms from a single, easy-to-understand specification model.