real-value modelling


June 29, 2015

FastSpice update improves parallelism and adds wreal support

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
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September 2, 2014

IoT mixed signal design: keep everything in the green

ARM and Cadence have teamed up to show how system-level and implementation-level representations of a mixed-signal design can be linked together and kept in sync as the project progresses.
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June 10, 2014

Verilog-AMS release adds to power-aware analog modeling

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
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January 14, 2014

Cadence updates Incisive with formal, CRV, wreal additions

Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
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October 8, 2013

Wreal and Open Access star in mixed-signal summit

Real-value modelling and flows using the Open Access database will be among the focus topics of Cadence's Mixed-Signal Technology Summit on 10 October.
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August 12, 2013

CDNLive Boston to tackle mixed-signal design, host exhibit

Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
May 15, 2012

Analog designers ‘need to use digital tools’

Designers working on mixed-signal circuits will benefit from using digital tools, Cadence's SVP of R&D for custom design said at CDNLive EMEA today. But for those who don't a faster fast Spice is on its way.

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