Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
ARM and Cadence have teamed up to show how system-level and implementation-level representations of a mixed-signal design can be linked together and kept in sync as the project progresses.
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Real-value modelling and flows using the Open Access database will be among the focus topics of Cadence's Mixed-Signal Technology Summit on 10 October.
Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
Designers working on mixed-signal circuits will benefit from using digital tools, Cadence's SVP of R&D for custom design said at CDNLive EMEA today. But for those who don't a faster fast Spice is on its way.
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