reference flow


October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 9, 2012

TSMC updates reference flows for 20nm and CoWoS

TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).


Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations:

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