Mythic


March 4, 2022

Verification engineers look to better skills to beat schedules

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
October 28, 2021

Emulation’s scheduling challenge

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: , , ,
February 12, 2020

AI processor company opts for Analog FASTSPICE and Symphony

Mythic will use the Mentor tools for its analog-targeted intelligence processing units.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors