DAC 2021 Preview: Siemens EDA

Siemens EDA will be present across the conference program and exhibition during next month’s physical edition of the Design Automation Conference  (DAC 2021) at the Moscone Center West in San Francisco (Dec 5-9).

Please note these highlights are primarily for delegates attending the conference on site. See the note at the end of this article if you are planning to attend Virtual DAC.

Siemens EDA experts will deliver five conference papers and 11 posters during the conference, host a tutorial and a designer track panel and offer five DAC Pavilion presentations. These are listed below with links to further information on each, as well as information on customer presentations.

The company itself will be present across four DAC 2021 exhibition booths. Its main presence will be on stand #2521. Meanwhile, formal and functional verification specialist OneSpin, acquired by Siemens earlier this year, will be present at booth #1539 and Siemens Cloud will be at booth #1246. The company will also be in the dedicated zone for companies supporting the open-source RISC-V processor core (booth B7)

A full list of Siemens EDA conference activities can also be found here, including information on its activities at two events collocated with DAC 2021, Semicon West and the RISC-V Summit as well as information on how to attend dedicated sessions at its main stand.

Siemens EDA activities at DAC 2021

DAC Pavilion Sessions

The Pavilion for DAC 2021 can be found on Level 2 of the Moscone West exhibition area.

Digitalization—the return to outsize growth for the semiconductor industry

10:15am – 11:15am PST, Monday, Dec. 6th

Handling SoC Verification: Changing the Paradigm in Verification Approaches

3:00pm – 3:45pm PST, Tuesday, Dec. 7^th

Design and Verification Engineer 2.0: A New Generation or a Pipe Dream?

2:00pm – 2:45pm PST, Wednesday, Dec. 8th

Conference Papers

Please click the link for up-to-date information on the time and room for each paper, as well as the full a abstract.

• Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
• What can chip design learn from the software world?
• Mitigating Variability Challenges of IPs for Robust Design
• Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks
• What can chip design learn from the software world?

Designer Track Panel

Sessions in this track will take place in dedicated theaters on Level 2 of Moscone West.

UVM: Where the Wild Things Are

10:30am – 12:00pm PST, Wednesday, Dec. 8^th

Tutorial

Please click the link below for full details on the location of the tutorial

Design and Consumption of IPs for Fail: Safe Automotive ICs

1:30pm – 5:00pm PST, Monday, Dec. 6^th

DAC Design Infrastructure Alley Presentation

Sessions in this track will take place in the Design-on-Cloud Theater on Level 1 of Moscone West

Siemens EDA Cloud Offerings

3:30pm – 4:15pm PST, Monday, December 6^th

Posters

Posters will be displayed for discussion with their authors on Level 2 of Moscone West at the following times: 5:00pm – 6:00pm PST on Tuesday, Dec. 7th and 6:00pm – 7:00pm PST, Wednesday, Dec. 8th

• Verifying Reset and Power Domains Together
• Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools
• Algorithm to RTL: A Faster Path to Implementation
• A Highly Reusable Generic UVM for Soft Processors​
• Accelerating advanced node ramp up and robust design enablement for leading edge SoC designers​
• Accelerating Standard Cells Variation-Aware Characterization Methodology with Machine Learning Techniques​
• Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools​
• Efficient High-Sigma Verification of Standard Cell Libraries​
• Preventing Gate-level Glitches on Clock: Domain Crossing Paths​
• Structural Analysis for RDC with Set-Reset flop​
• Verification Methodology for High-Resolution, High-Speed CMOS Image Sensor SoC – Leveraging Innovations in EDA Tools​

Customer sessions

Please click the link for the presentations that interest you to receive up-to-date information on the time and room for each paper, as well as the full abstract. Posters will be displayed for discussion with their authors on Level 2 of Moscone West

 Customer presentations include:

• Ensuring Completeness of Formal Verification with GapFree: Are we done yet? (Sandia National Labs)
• Efficient High-Sigma Verification of Standard Cell Libraries (Arm)

Customer poster sessions include:

• Beyond Lint (ICsense)
• Formal Verification of Safety Mechanisms (Infineon Technologies, Technische Universität Kaiserslauten)

This post will be updated with further information on the company’s activities during Virtual DAC (Dec 13-Jan1), which has been organized for design professionals who cannot be physically present due to various international Covid-19 restrictions. Registration for DAC 2021 and Virtual DAC is available now at the main conference website.