Siemens brings emulation and prototyping together in hardware-assisted verification

By TDF Staff |  No Comments  |  Posted: March 26, 2021
Topics/Categories: Blog - EDA  |  Tags: , , , , , ,  | Organizations: , ,

Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support using field programmable gate arrays (FPGAs).

There are three families. Veloce HYCON (HYbrid CONfigurable) is intended for use as a virtual platform for software-oriented verification. Veloce Strato+ represents a capacity upgrade to the Veloce Strato hardware emulator, scaling up to 15 billion gates. For FPGA prototyping Siemens is offering Veloce Primo, an internally developed enterprise prototyping system, as well as Veloce proFPGA for desktop FPGA prototyping based on a modular architecture.

Siemens says it has developed a seamless approach to managing verification using the different hardware elements. Customers can build and test virtual SoC models early in the cycle and during IP integration to run real-world firmware and software on Veloce Strato+. This provides the best visibility of hardware for debugging. Customers can then move the same design to Veloce Primo to validate the software-hardware interfaces and execute application-level software while running closer to actual system speeds. Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models to maximize the reuse of verification collateral, environment and test content. Siemens says this is a prerequisite for a seamless methodology.

Siemens' Veloce platform is intended to support the full range of hardware-assisted verification platforms

Image Siemens' Veloce platform is intended to support the full range of hardware-assisted verification platforms

“As we enter the new semiconductor mega-cycle, the era of software-centric SoC design requires a dramatic change in functional verification systems to address new requirements,” said Ravi Subramanian, senior vice president and general manager of Siemens EDA. “The introduction of the next-generation Veloce system that addresses these key new requirements is a direct result of the focused investment from Siemens to offer our customers a complete, integrated system with a clear roadmap for the next decade. With today’s announcement, we are establishing a new standard for a system that is capable of supporting the new verification requirements across a diverse set of industries-spanning computing and storage, AI/ML, 5G, networking, and automotive.”

To support its higher capacity, Siemens has moved to a proprietary 2.5D chip, called Crystal 3, which helps increases system capacity by 1.5x over the previous Veloce Strato system. The maximum 15 billion gate capacity, which the company says is the largest effective capacity available today, is now in use at multiple Veloce Strato+ customers.

“AMD utilizes Veloce Emulation platforms as part of our pre-silicon verification and validation solutions,” said Alex Starr, corporate fellow and methodology architect at AMD “We are delighted to have worked with Siemens to pioneer high-capacity Veloce Strato+ system deployment at AMD. Furthermore, we’re excited to see second and third generation AMD EPYC processors qualified for use with Veloce Strato and Veloce Strato+ platforms.”

For prototyping, enterprise-level Veloce Primo system can scale up to 320 FPGAs, using the Xilinx UltraScale+ VU19P devices, and offers alignment between emulation and prototyping. Veloce Primo also supports both virtual (emulation offload) and in-circuit-emulation (ICE) use-cases.

Through an OEM agreement with Pro Design, Siemens supports desktop prototyping with the Veloce proFPGA. It supports capacity requirements from 40 million gates to 800 million gates based on FPGAs such as the Intel Stratix 10 GX 10M and the Virtex UltraScale+ VU19P.

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