EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
3DIC
TSMC updates reference flows for 20nm and CoWoS
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
Event alert: TSMC Open Innovation Platform
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
Strained silicon beats TSV stress in 3DICs
Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
Synopsys builds 3D into tool portfolio
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
DATE notebook: EDA for the rest of us
Old processes don't necessarily equate to old tools, panelists argued at DATE, especially when a lot of future work will be done on more-than-Moore, 3DIC technologies.
DATE notebook: Stack those servers high
Concern over energy consumption could be the key to European companies moving back into the compute server market – or at least that's what the European Commission and researchers think is possible as social networks, GPS data and public video cameras pour data into a growing collection of online storage banks.
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