TSMC updates reference flows for 20nm and CoWoS

By Chris Edwards |  1 Comment  |  Posted: October 9, 2012
Topics/Categories: Design to Silicon, Blog - EDA  |  Tags: , , ,  | Organizations:

TSMC has released two reference flows – one for its 20nm process and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).

The 20nm process flow is based around place and route tools that have been made double-patterning aware, as well as timing, physical verification and design for manufacturing (DFM) tools. The recommended double-patterning techniques include support for pre-coloring – to define which portions of each cell should go on each mask layer – and a new RC extraction methodology.

The CoWoS reference flow is intended to allow a smooth transition to 3D IC (Guide) with few changes in existing methodologies. The flow covers the way in which solder bumps are placed and routed, interconnections as well as extraction and signal-integrity analysis of high-speed interconnects between dies. Also covered is the thermal analysis from chip to package to system and a methodology for testing at the die and stack levels.

Also released is a custom design reference flow for 20nm. It includes a direct link to simulators for the verification of voltage-dependent DRC rules. The related RF reference-design kit provides new high-frequency design guidelines. These comprise 60GHz RF model support, integrated-passive device support and electromagnetic (EM) characterization.

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