DATE notebook: EDA for the rest of us

By Chris Edwards |  3 Comments  |  Posted: March 14, 2012
Topics/Categories: Commentary, Conferences, Design to Silicon, Digital/analog implementation, Blog - EDA  |  Tags: , , ,

“I understand the feeling that when we talk we place a lot of emphasis on 20nm and the leading-edge processes. We are already talking about finFETs at 14nm,” Antun Domic, general manager of Synopsys’ implementation group, said as he introduced the work that his company is doing to support designers working way back from the bleeding edge of the process technology curve. The venue was a panel session at DATE on what the EDA vendors could do to support designs on older processes, and what users such as Robert Bosch and Infineon Technologies expect of them.

Joe Sawicki, general manager of the design-to-silicon division at Mentor Graphics, pointed out that in term of design starts trailing-edge processes are expected to account for a larger share of the total through 2015, although the growth in that balance is not huge. He showed figures from International Business Strategies that predicted, as a percentage of total design starts, an increase from 22 per cent in 2010 for trailing edge technologies – in this case, designs on processes older than 90nm – to 28 per cent in 2015.

Domic argued that developments on new tools have a lot to give for older nodes. He presented an analysis of how consecutive releases of the company’s tools deal with older designs – the company keeps a number of test design on hand for use in regression testing of new releases.

“Using the latest releases of the tools, we see a significant decrease in runtime,” Domic claimed, pointing to at least a two-fold improvement on designs of several hundred thousand gates over five releases from around 2006 to 2010. Routing saw a big drop in the latest release, due largely to the use of multicore processing for the routing engine.

But it’s not just runtime, Domic argued. Some designs being done on older processes, such as the perenially popular 180nm, do not necessarily mesh well with older tools. He pointed to a microcontroller from an unnamed customer based around ARM’s M0.

“The design contains 10 voltage regions and a significant analog portion. This kind of design would not have been possible with the Synopsys tools of three to four years ago. The multivoltage capabilities enabled these kinds of things,” Domic explained.

In recent years, custom design and automated place-and-route have become more closely tied, Domic added. And custom designs come into the digital place-and-route tools with properties that tell the automated algorithms to leave carefully routed traces – for matched pairs, for example – well alone.

A third area where trailing-edge design is becoming the leading edge is in 3D ICs. “The amount of work that EDA has been doing for this is larger than people expect. And this is one of the areas in my opinion being highlighted as potential for the older semiconductor technologies,” Domic said.

Sawicki agreed that the more-than-Moore 3D IC technologies – or the 2.5D designs based on interposers – presented an opportunity for new tools and old processes to become better acquainted. And older processes, because of their low cost, will participate heavily in applications beyond computing and communications. “Silicon will be everywhere,” said Sawicki.

“If you have a child of under five, you’ve got to wonder whether they will drive a car rather than a car driving them. When you start to have a car that drives you, reliability becomes very important,” Sawicki added – leading to greater demand for tools that can deliver assurances on safety and reliability.

The automotive panel in executive track the day before highlighted areas where the tools industry has yet to respond. Sawicki pointed out areas in current IC design tool development that could be applied to these older technologies, particularly where reliability is a major concern.

One trend, said Sawicki, “is an emerging physical verification technology to do multidomain verification and look for reliability issues. A second trend is a focus on test to reduce defects per million. And a third is to tie that all together into a system where we can investigate the potential for improving yield and analysing returned die.”

Rainer Kress of Infineon Technologies said EDA companies should not forget about the legacy tools and do more to ensure that they remain interoperable with the newer products. He highlighted one particular problem with designs on older technologies – they often have a lot of circuits and IP that were developed on older versions and process design kits (PDKs). When imported into newer flows, the IP turns out with tangible differences in layout and behaviour, which demands either requalification or finding a way to use older tools to recreate the IP and then import the designs at the physical level – and the loss of design intent that this entails – into the newer flows.

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