October 18, 2021
Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.
October 7, 2021
Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
July 28, 2021
A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
July 15, 2021
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
June 4, 2021
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
August 25, 2020
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
July 21, 2020
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
July 13, 2020
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
October 9, 2018
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
July 11, 2018
Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.