DATE notebook: Stack those servers high

By Chris Edwards |  No Comments  |  Posted: March 13, 2012
Topics/Categories: Blog Topics, Conferences, Blog - Embedded  |  Tags: , , , , ,

Concern over energy consumption could be the key to European companies moving back into the compute server market – or at least that’s what the European Commission and researchers think is possible as social networks, GPS data and public video cameras pour data into a growing collection of online storage banks.

Speaking at the Design Automation and Test in Europe (DATE) conference in Dresden on Tuesday, Rolf Riemenschneider, research program officer for embedded systems and control at the European Commission, said the new wave in high-performance computing “is a window of opportunity for Europe”.

Riemenschneider added: “We see not just an explosion of data but an explosion of real-time online data. We see more interaction between machines and between human-interface devices.”

The panel took place on the day that ARM launched its smallest 32bit core to date – the M0+ – with a minimal two-stage pipeline aimed at the kind of ambient-intelligence devices that Riemenschneider believes will capture and record data to be mined by a cloud of servers. “The world will become a global system of systems.”

The UK company’s processor cores are not just envisaged as data collectors at the edge of the network but the server processors themselves, with researchers from the CATRENE group, TU Delft and the University of Ghent using ARM-based designs to test architectures that replace high-end Intel Xeon with very many more individually lower-power ARM cores.

Koen Bertels of TU Delft talked about a machine implementing 20 cache-coherent but relatively simple dual-issue ARMs in a ‘pod’, assembled into a much larger non cache-coherent machine of many pods that might work on one application but will probably be dedicated to a collection of much smaller tasks. For these uses, a single Xeon has to context-switch too many times to be efficient, claimed Luigi Grasso, a CATRENE fellow, constantly leading to cache buffers being flushed out to main memory as new entries are loaded for completely different applications.

“Virtualization is an old technology. What we want is physicalization. Imagine hundreds of small cores running on a multicore SoC. Each single core only runs a few applications. This means the cache on each will be cold and the performance overall will be better,” Grasso claimed.

Grasso argued that the key technologies that will be important will not be so much Moore’s Law as the more than Moore system-in-package technologies and photonic interconnects as well as solid-state storage, with flash as near-line mass storage and MRAM, resistive RAM or memristors being used for storage closer to the processor.

“By 2020, flash will be cheaper than hard drives,” Grasso claimed.

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