Event alert: TSMC Open Innovation Platform

By Paul Dempsey |  2 Comments  |  Posted: October 9, 2012
Topics/Categories: Blog Topics, Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , ,  | Organizations: , ,

TSMC’s Open Innovation Platform Ecosystem Forum takes place at the San Jose Convention Center on Tuesday, October 16th, starting at 9.00am – and you must pre-register to attend the event.

We’ll be there providing updates on the day and immediately afterwards, but if you can make it, it certainly looks worth your time.

A quick glance at the agenda shows the foundry looking to push its latest technologies hard with three main themes across the technical sessions being 20nm, silicon interposer (specifically its Chip-on-Wafer-on-Substrate/CoWoS) technology and IP. There will also be a large side order of double patterning.

Alongside TSMC’s own keynotes framing the latest roadmap highlights, an ARM speaker will also address the path to FinFETs.

If you want to brief yourself on some of the conference issues before the event, check out our guides on both 2.5 D, 3D and 5.5D and double pattering, as well as articles from Synopsys’ Antun Domic and Andy Biddle, and Mentor Graphics’ Michael Buehler-Garcia that set the scene for 20nm.

There are still further valuable pointers in our recent interviews with Synopsys’ chairman and CEO Aart de Geus and Mentor Design-to-Silicon VP Joe Sawicki.

We hope to meet some of you in Santa Clara, but if you can’t make it, make sure to check back next Tuesday and Wednesday for our continuously updated event page. It will go live on Tuesday afternoon.

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