EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

By Luke Collins |  1 Comment  |  Posted: October 16, 2012
Topics/Categories: Commentary, Conferences, Blog - EDA  |  Tags: , , , , , , , ,  | Organizations: , , , , ,

At its Open Innovation Platform meeting in San Jose today, TSMC put meat on the bones of its announcement last week of reference design flows for the TSMC 20nm digital and analog, and 3DIC (Guide) processes. The design tool and IP industries have stepped up with a series of announcements of their own, detailing where their offerings fit into the TSMC flow.

What’s difficult about designing at 20nm? Back at DAC in June, Michael Buehler-Garcia, senior director of marketing for Calibre design solutions at Mentor Graphics, was emphasising double patterning, tool performance given the increased use of fill, and design for reliability.

More recently, Antun Domic, senior vice president and general manager of the implementation group at Synopsys, has been focusing on the complexity, physics and economics of the 20nm node.

Here’s what we know so far about the tool and IP announcements being made at TSMC’s OIP:

 

TSMC 20nm digital flow

Cadence’s Encounter RTL-to-GDSII now supports 20nm rules, and what it calls FlexColor double-patterning technology to enable correct-by-construction placement and routing. The Encounter RTL Compiler and the GigaOpt optimization technology for the Encounter Digital Implementation System have also been updated for 20nm designs.

For signoff, the Cadence Encounter Timing System offers advanced waveform modeling and multi-valued SPEF for double-patterning RC extraction. Cadence QRC Extraction delivers a DPT-aware technology for extracting design corners from both LEF/DEF and GDSII flows.

The Cadence Physical Verification System supports 20nm double-patterning and incremental DRC correction, and TSMC rule decks are available for it.

For more detailed work, the Encounter Power System provides topology-dependent electromigration rules, and Litho Physical Analyzer and Litho Electrical Analyzer have been updated with 20nm models for hotspot analysis and repair.

Finally, TSMC has adopted Cadence technology for its Custom Design Reference Flow, which demonstrates a methodology for designing custom and digitally assisted analog circuits through common technology setup and integrated concurrent analog and digital layout.

Here’s the press release.

 

Mentor Graphics has added 20nm support features such as DRC/DP-aware routing, litho pattern matching, fixing and timing closure, coloring-aware pin access, critical net routing, and DP-aware placement to Olympus-SoC.

The tool also provides database support for DP and pre-coloring, post-route dynamic power optimization, intelligent gate sizing and Vt assignment, voltage-dependent design spacing rules, in-chip overlay, dummy typical critical dimension and boundary cell insertion.

The Calibre nmDRC platform is updated to support double-patterning anchoring and pre-coloring, double-patterning  design rule checking, voltage-dependent checking and real-time graphical ‘error rings’ to help speed up the resolution of coloring conflicts.

Mentor and TSMC  worked together on a way to fix reliability issues such as electrostatic discharge (ESD) and latch-up. Calibre PERC  checks for potential sources of electrical failure, showing the user circuit connectivity, topology, physical layout and design rules all at once.

Calibre SmartFill has been updated to reduce the risk of differences between pre- and post-fill timing analysis. Calibre LFD now works with the TSMC Unified DFM Engine, to bring pattern matching technology to the task of detecting litho hot spots.

The Calibre xACT 3D extraction tool has been updated to handle new complexities such as the misalignment of double-patterning masks.

The Tessent silicon test tools now support user-defined fault models and cell-aware test pattern generation, which allows test engineers to improve the coverage and quality of IC test. Cell-aware testing detects bridging and open defects internal within cells, which are otherwise undetected by conventional fault models. Tessent TestKompress generates patterns to target these additional defects.

Here’s the press release.

 

Synopsys has updated the Galaxy Implementation Platform to support TSMC’s 20nm design rules and models, as well as to make it aware of the issues that surround the use of double patterning lithography for critical layers.

IC Compiler is updated to enable designers to create layout that comply with the needs of double patterning and which can be reliably decomposed (split on to two masks) during manufacturing.

(See more from Synopsys Fellow Tong Gao on this topic here.)

IC Validator gets a decomposition (coloring engine) to perform double-patterning checks during design, and to fix violations through links to IC Compiler.

(More on that here.)

PrimeTime adds double-patterning-aware variation analysis that includes multi-valued SPEF model variation and its impact on timing.

StarRC provides silicon-calibrated modeling to account for mask misalignment due to double patterning and non-color and color-aware extraction for accurate, high-performance design.

Here’s the press release.

 

TSMC 20nm analog flow

Cadence’s Virtuoso tools have been updated to handle key 20nm constraints such as G0 rules, interactive coloring for color-aware layout, a constraint-driven pre-coloring flow, odd-cycle loop prevention and detection, P-cell abutment and support for local interconnect layers.

Cadence’s Integrated Physical Verification System integrates the Cadence Physical Verification System within the Virtuoso platform, so that designers can get feedback about their layouts  as they work.

Here’s the press release.

 

Mentor’s Pyxis IC Station for custom design gets a new sensitivity analysis feature to work with its Eldo fast SPICE simulation products, and voltage-dependent design-rule checking to work with Calibre nmDRC, Calibre nmLV and Calibre RealTime products.

Calibre RealTime, which provides design rule checking and guidance on possible fixes during custom layout editing, has been extended to support full sign-off verification of 20nm rules, including double-patterning checking and debugging aids, and voltage-dependent checks.

Here’s the press release.

 

TSMC CoWoS 3DIC flow

Cadence has done a test design that integrates multiple die using TSMC’s CoWoS technology to prove its 3DIC design flow. The design includes a Wide I/O memory controller and PHY IP.

Tools now validated for the flow include the Encounter RTL-to-signoff and Virtuoso custom/analog platforms. The Cadence system-in-package products, and recently acquired Sigrity power-aware chip/package/board signal-integrity solution have also ben validated.

TSMC’s unique CoWoS combo bump cells, which simplify bump assignment, are now supported automatically in the Cadence Encounter Digital Implementation System, QRC Extraction, and Cadence Physical Verification System. The CoWoS reference flow is supported with a CoWoS design kit and silicon validation results from a TSMC test vehicle.

Here’s the press release.

 

Taiwan’s Industrial Technology Research Institute has used the Cadence flow to implement, analyze, and verify a wide I/O memory stack with through-silicon vias (TSVs).

Cadence technologies deployed include Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Test, Encounter Timing System, Encounter Power System, the Cadence Physical Verification System, and QRC Extraction.

Here’s the press release.

 

Mentor has a reference flow for TSMC’s CoWoS offering, based on both the  Olympus-SoC place and route system for digital designs and the Pyxis IC Station for custom layouts.

Olympus-SoC supports probe-pad routing for both micro bumps and C4 bumps, as well as routing between combo bumps. Inter-die design rule and layout-vs-schematic checks are done  during layout construction to help ensure rapid signoff.

Pyxis IC Station can be used to route redistribution layers generate ground planes, with 45 degree routes to vias.

The Calibre 3DSTACK sign-off tool gets capabilities to verify physical offset, rotation, and scaling at the die interfaces. It can also trace connectivity and extract interface parasitics to enable multi-die performance simulation.

There’s also an integration between Calibre and the FloTHERM 3D computational fluid dynamics software to model temperature variation across the CoWoS design.

The Tessent test tool gets additional capabilities to improve overall 3DIC yeidl including pre-bond testing of TSVs and I/Os; test generation for shorts or opens between logic die, and between logic and DRAM; plus enhanced memory BIST.

Here’s the press release.

 

Synopsys has  released enhanced versions of its Galaxy Implementation Platform tools for physical implementation, parasitic extraction, physical verification and timing analysis in support of the TSMC CoWOS roll-out.

There are updates to IC Compile for multi-die physical implementation with support for placement, assignment and routing of microbumps, thru-silicon vias, probe-pad and C4 bumps. Also support for combo bump cells enabling flexible bump assignment; microbump alignment checks; redistribution layer and signal routing, and power mesh creation on CoWoS interconnection layers.

In analysis and sign-off, the Hercules layout vs schematic checker can now check for connectivity between stacked die, while the StarRC Ultra parasitic extractor gains support for TSV, microbump, RDL and signal routing metal. PrimeTime gets an update to handle timing analysis of multi-die systems.

Here’s the press release

 

20nm IP

Analog Bits has taped out a chip in TSMC’s 20nm HKMG process, and is now offering a  mixed-signal design kit for early adopters.

The kit includes SERDES, temperature sensors, PLLs and other IP blocks.

Here’s the press release.

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